1. Field of the Invention
The present invention relates to programming of a multi-level phase change memory cell and in particular to a programming scheme for fast multi-level recording.
2. Description of Related Art
Phase change memories, which are also known as PCM, PRAM, PCRAM, Chalgogenide RAM and C-RAM, are non-volatile solid state memories which can satisfy the needs for a random access memory as well as mass data storage. These phase change memories use the unique behavior of a phase change material such as chalgogenide glass which can be switched between two states, i.e. a crystalline state and an amorphous state. In the amorphous state the phase change material includes a high resistance whereas in the crystalline state the phase change material has a low resistance. Since, in the crystalline and amorphous state the phase change material has different electrical resistivity, this physical property can be used to store data. The amorphous state, which has a high resistance, can be used to represent a logical zero, whereas the crystalline, low resistance state can be used to represent a logical one. A phase change memory cell can be programmed to include more than two different resistance levels. A memory cell can, for example, be programmed to have four different levels of resistance spanning the range, for example, from 10 kΩ to 10 MΩ. The low resistance level of 10 kΩ could correspond to two logical bits 00, the next resistance level of 100 kΩ could represent two logical bits 01, the next higher resistance level of, for example, 1 MΩ could represent a logical bit combination of 10, and the highest resistance level of 10 MΩ could represent logical bits 11. Accordingly, a phase change memory cell can form a multi-level phase change memory cell having multiple resistance levels to store more than one bit in a single memory cell. The capability of multi-level phase change memory cells for storing multiple bits in one cell increases the effective storage density of a phase change memory. Each of the resistance levels or states can have different physical properties that can be measured during read operations.
The storage of multiple resistance levels in a multi-level phase change memory cell is challenging, however, due to manufacturing process variability as well as intra-cell and inter-cell material parameter variations. For example, feed forward direct schemes are known that use a sequence of pulses of varying shapes such as described by J. B. Philipp and T. Happ in U.S. Pat. No. 7,372,725 B2, “Integrated Circuit Having Resistive Memory.” In these cases, process and parameter variabilities may cause deviations of the achieved resistance levels from their intended resistance values. Accordingly, iterative programming schemes with multiple write-verify steps, which have been proposed, for example by J. B. Philipp, T. Happ, and M. H. Lee in U.S. Pat. No. 7,564,710 B2, “Circuit for Programming a Memory Element,” may reach the desired resistance levels within a multi-level phase change memory cell. Iterative programming schemes, however, can be very time-consuming, because switching between read and write circuitry is necessary.